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REVISIONS LTR A B DESCRIPTION Add "Changes in accordance with NOR 5962-R115-92." Add software data protection. Increase data retention to 20 years, minimum. Add device types 08 through 16. Remove tests tDHWL, tWHDX, and ESDS requirements from drawing. Add "Changes in accordance with NOR 5962-R071-95." Updated boilerplate paragraphs. ksr DATE (YR-MO-DA) 92-01-27 93-07-21 APPROVED M. A. Frye M. A. Frye
C D
95-02-14 05-04-15
M. A. Frye Raymond Monnin
The original first page has been replaced. REV SHEET REV SHEET REV STATUS OF SHEETS PMIC N/A D 15 D 16 D 17 D 18 REV SHEET PREPARED BY Kenneth Rice D 19 D 20 D 21 D 1 D 22 D 2 D 23 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A
CHECKED BY Raymond Monnin APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 88-08-29
MICROCIRCUIT, MEMORY, DIGITAL, CMOS 32K X 8 EEPROM, MONOLITHIC SILICON
SIZE A SHEET CAGE CODE
REVISION LEVEL D
67268
1 OF 23
5962-88525
5962-E286-05
DSCC FORM 2233 APR 97
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1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88525 Drawing number 01 Device type (see 1.2.1) X Case outline (see 1.2.2) A Lead finish (see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Generic number See 6.6 Circuit function Access time Write speed Write mode End of Write Indicator Endurance Software data protect No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes
(32K X 8 EEPROM) 350 ns 10 ms byte/page 300 ns 10 ms byte/page 250 ns 10 ms byte/page 200 ns 10 ms byte/page 250 ns 10 ms byte/page 150 ns 10 ms byte/page 150 ns 3 ms byte/page 150 ns 10 ms byte/page 350 ns 10 ms byte/page 300 ns 10 ms byte/page 250 ns 10 ms byte/page 200 ns 10 ms byte/page 250 ns 10 ms byte/page 150 ns 10 ms byte/page 150 ns 3 ms byte/page 150 ns 10 ms byte/page
DATA polling 10,000 cycles
DATA polling 10,000 cycles DATA polling 10,000 cycles DATA polling 10,000 cycles DATA polling 100,000 cycles DATA polling 10,000 cycles DATA polling 10,000 cycles DATA polling 100,000 cycles DATA polling 10,000 cycles DATA polling 10,000 cycles DATA polling 10,000 cycles DATA polling 10,000 cycles DATA polling 100,000 cycles DATA polling 10,000 cycles DATA polling 10,000 cycles DATA polling 100,000 cycles
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter U X Y Z Descriptive designator See figure 1 GDIPI-T28 or CDIP2-T28 CQCC1-N32 CDFP4-F28 Terminals 128 28 32 28 Package style Grid array Dual-in-line Rectangular leadless chip carrier Flat package
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
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1.3 Absolute maximum ratings.
1/ -0.3 V dc to +6.25 V dc -65C to +150C 1.0 W +300C +175C See MIL-STD-1835 -0.3 V dc to +6.25 V dc 10 years (minimum) 10,000 cycles/byte (minimum) 100,000 cycles/byte (minimum) 15.0 V dc
Supply voltage range (VCC) ............................................................................ Storage temperature range ............................................................................ Maximum power dissipation (PD).................................................................... Lead temperature (soldering, 10 seconds) ..................................................... Junction temperature (TJ) 2/........................................................................... Thermal resistance, junction-to-case (JC)..................................................... Input voltage range (VIL, VIH) .......................................................................... Data retention................................................................................................. Endurance: Types 01-04, 06, 07, 09-12, 14, 15 .............................................................. Types 05, 08, 13 ,16..................................................................................... Chip clear voltage (VH) ................................................................................... 1.4 Recommended operating conditions. 1/ Supply voltage range (VCC) ............................................................................ Case operating temperature range (TC) ......................................................... Input voltage, low range (VIL).......................................................................... Input voltage, high range (VIH)........................................................................ 2. APPLICABLE DOCUMENTS
+4.5 V dc to +5.5 V dc -55C to +125C -0.1 V dc to +0.8 V dc +2.0 V dc to VCC +0.3 V dc
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 List of Standard Microcircuit Drawings. Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MILPRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MILPRF-38535 is required to identify when the QML flow option is used. 1/ 2/ All voltages are referenced to VSS (ground). Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883.
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3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). See 3.2.3.1 and 3.2.3.2 3.2.3.1 Unprogrammed or erased devices. The truth table for unprogrammed devices shall be as specified on figure 3. 3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EEPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EEPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4.3. 3.10.2 Programmability of EEPROMS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.4.2. Software data protect procedures shall be as specified in 4.4.5. 3.10.3 Verification of erasure or programmability of EPROMS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of reading the device per the procedures and characteristics specified in 4.4.4. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot.
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TABLE I. Electrical performance characteristics. Test Symbol ICC1 ICC2 ICC3 IIH IIL IOHZ 2/ IOLZ 2/ VIL VIH VOL VOH IOE Conditions -55C TC +125C VSS = 0 V, 4.5 V VCC 5.5 V unless otherwise specified 1/ CE = OE = VIL, WE = VIH all I/O's = 0 mA, Inputs = VCC = 5.5 V, f = 1/tAVAV (minimum) CE = VIH, OE = VIL all I/O's = 0 mA Inputs = VCC -0.3 V CE = VCC -0.3 V all I/O's = 0 mA, Inputs = VIL to VCC -0.3 V VIN = 5.5 V VIN = 0.1 V VOUT = 5.5 V, CE = VIH VOUT = 0.1 V, CE = VIH IOL = 2.1 mA, VIH = 2.0 V VCC = 4.5 V, VIL = 0.8 V IOH = -400 A, VIH = 2.0 V VCC = 4.5 V, VIL = 0.8 V VH = 13 V Group A subgroups 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 Device Limits types Min Max All All All All All All All All All All -10 -10 -10 -10 -0.1 2.0 2.4 -10 80 3 350 10 10 10 10 0.8 VCC + 0.3V 0.45 100 Unit
Supply current (active)
mA mA A A A A A V V V
Supply current (TTL standby)
Supply current (CMOS standby)
Input leakage (high) Input leakage (low)
Output leakage (high)
Output leakage (low) Input voltage low Input voltage high Output voltage low
Output voltage high
All
V
OE high leakage (chip erase)
All
A
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. Symbol Input capacitance CI 3/ 4/ Output capacitance CO 3/ 4/ Read cycle time tAVAV 5/ Address access time tAVQV 5/ Chip enable access tELQV 5/ time Output enable access tOLQV 5/ time Chip enable to output tELQX 4/ in low Z 5/ Chip disable to tEHQZ 4/ output in high Z 5/ Output enable to tOLQX 4/ output in low Z 5/ Output disable to tOHQZ 4/ output in high Z 5/ Output hold from tAXQX 4/ address change 5/ Test See footnotes at end of table. Conditions -55C TC +125C VSS = 0 V, 4.5 V VCC 5.5 V unless otherwise specified 1/ VIN = 0 V, VCC = 5.0 V TA = +25C, f = 1 MHz See 4.3.1c VOUT = 0 V, VCC = 5.0 V TA = +25C, f = 1 MHz See 4.3.1c See figure 4 Group A subgroups 4 4 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 Device Limits types Min Max All 10 All 10 01,09 350 02,10 300 03,05,11,13 250 04,12 200 06-08,14-16 150 01,09 350 02,10 300 03,05,11,13 250 04,12 200 06-08,14-16 150 01,09 350 02,10 300 03,05,11,13 250 04,12 200 06-08,14-16 150 01-03,05 09-11,13 100 04,06,07,08 12,14,15,16 80 All 10 01,02,09,10 80 03-08,11-16 60 All 10 01,02,09,10 80 03-08,11-16 60 All 0 Unit
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
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TABLE I. Electrical performance characteristics - Continued. Test Symbol tWHWL1 tEHEL1 5/ tAVEL 5/ tAVWL tELAX 5/ tWLAX tWLEL 5/ tELWL tEHWH 5/ tWHEH tOHEL tOHWL 5/ tEHOL tWHOL 5/ tELEH tWLWH 5/ 6/ tDVEH tDVWH 5/ tDVWL 4/ tDVEL 5/ tEHDX tWHDX 5/ tWHWL2 5/ 6/ Conditions Group A subgroups -55C TC +125C VSS = 0 V, 4.5 V VCC 5.5 V unless otherwise specified 1/ See figure 5 or 7 9,10,11 as applicable See figures 5, 6, or 7 9,10,11 as applicable 9,10,11 9,10,11 9,10,11 See figure 5 or 7 as applicable 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 Device types 01-06, 08-14, 16 07,15 All All All All All All All Limits Min Max 10 3 20 150 0 0 20 20 .150 50 10 .20 1 10 149 Unit
Write cycle time
ms
Address set-up time Address hold time
ns ns
Write set-up time
ns
Write hold time
ns
OE set-up time
ns ns s
OE hold time
WE pulse width
Data set-up time
All
ns
Delay to next write
All
s
Data hold time
All
ns
Byte load cycle
All
s
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued. Test Symbol tWHEL tEHEL 5/ tELWL 5/ 5/ tOVHWL Conditions -55C TC +125C VSS = 0 V, 4.5 V VCC 5.5 V unless otherwise specified 1/ See figure 5 or 6 as applicable See figure 8 Group A subgroups 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 Device types All All All All All All All All Limits Min Max 650 5 5 5 5 12 10 13 210 Unit s s s s s V ms ms
Last byte loaded to data polling
CE setup time Output set-up time
CE hold time
tWHEH 5/ 5/ tWHOH VH 5/ 5/ tWLWH2
OE hold time High voltage Chip erase
WE pulse width for chip erase
tWLWH15/
1/ 2/ 3/ 4/ 5/
DC and read mode. Connect all address inputs and OE to VIH and measure IOLZ and IOHZ with the output under test connected to VOUT. All pins not being tested are to be open. Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits specified in table I. Tested by application of specified timing signals and conditions, including: Equivalent ac test conditions: Devices: All. Output load: 1 TTL gate and CL = 100 pF (minimum) or equivalent circuit. Input rise and fall times 10 ns. Input pulse levels: 0.4 V and 2.4 V. Timing measurements reference levels: Inputs: 1 V and 2 V. Outputs: 0.8 V and 2 V.
6/
During a page write operation the cycle time defined by tWLWH and tWHWL2 shall not be less than 1 s.
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NOTES: 1. Dimensions are in inches. 2. Metric equivalents are given for general information only.
Inches .002 .005 .008 .010 .012 .050 .067 .075 .100 .180 .551 .650
mm 0.05 0.13 0.20 0.25 0.30 1.27 1.70 1.90 2.54 4.57 14.00 16.51
FIGURE 1. Case outline.
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Device types Case outlines Terminal numbers 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7
CE
All U, X, Z Terminal symbols NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 NC I/O0 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 I/O6 I/O7
CE
Y
A10
OE
A11 A9 A8 A13
WE
A10
OE
NC A11 A9 A8 A13
WE
VCC ---------
VCC
FIGURE 2. Terminal connections.
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Mode Read Standby Chip clear Byte write Write inhibit Write inhibit
X = Don't care state.
CE
OE
WE
I/O DOUT High Z DIN = VIH Data in High Z/D out High Z/D out
Device type
VIL VIH VIL VIL X X
VIL X VH VIH VIL X
VIH X VIL VIL X VIH
All
FIGURE3. Truth table for unprogrammed devices.
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FIGURE 4. Timing waveforms.
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FIGURE 5.
CE controlled byte write programming waveform.
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FIGURE 6.
WE controlled byte write programming waveform.
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Note:
The page write operation of the device allows 2 to 64 bytes of data to be loaded into the device and then simultaneously written during the internal programming period.
FIGURE 7. Page write programming waveform.
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FIGURE 8. Timer chip clear waveform.
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NOTES: 1. 2. Software chip clear timings are referenced to WE or CE inputs, whichever is last to go low, and the WE or CE inputs, whichever is first to go high. The command sequence must conform to the page write timing.
FIGURE 9. Software chip clear algorithm (device types 09-16).
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NOTES: 1. 2. Software data protection timings are referenced to the WE or CE inputs, whichever is last to go low, and the
WE or CE inputs, whichever is first to go high.
The command sequence and subsequent data must conform to page write timing.
FIGURE 10. Set software data protect algorithm (device types 09-16).
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NOTES: 1. Reset software data protection timings are referenced to the WE or CE inputs, whichever is last to go low, and the WE or CE inputs, whichever is first to go high. 2. The command sequence and subsequent data must conform to page write timing.
FIGURE 11. Reset software data protect algorithm(device types 09-16).
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4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D or F. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. TA = +125C, minimum. Devices shall be burned-in containing a checkerboard pattern or equivalent.
(2) (3)
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. An endurance/data retention test prior to burn-in, in accordance with method 1033 of MIL-STD-883, shall be included as part of the screening procedure with the following conditions: (1) Cycling may be block, byte, or page at equipment room ambient temperature and shall cycle all bytes for a minimum of 10,000 cycles for devices 01-04, 06,07, 09-12, 14,15 and a minimum of 50,000 cycles for device 05,08,13, and 16. After cycling, perform a high temperature unbiased bake for 72 hours at +150C (minimum). The storage time may be accelerated by using higher temperature in accordance with the Arrhenius Relationship:
(2)
AF = acceleration factor (unitless quantity) = t1 / t2 T = temperature in Kelvin (i.e., t1+ 273) t1 = time (hrs) at temperature T1 t2 = time (hrs) at temperature T2 K = Boltzmanns constant = 8.62 x 10-5eV/K using an apparent activation energy (EA) of 0.6 eV.
The maximum storage temperature shall not exceed +200C for packaged devices or +300C for unassembled devices. (3) Read the data retention pattern and test using subgroups 1, 7, and 9 (minimum, e.g., high temperature equivalent subgroups 2, 8A, and 10 may be used) after cycling and bake, prior to burn-in. Devices having bits not in the proper state after storage shall constitute a device failure. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. b. c. Tests shall be as specified in table II herein. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. Subgroup 4 (CI and CO measurement) shall be measured only for the initial test and after process or design changes which may affect input or output capacitance.
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d.
Subgroups 7 and 8 shall include verification of the truth table.
4.3.2 Group C inspections. a. b. c. (1) End-point electrical parameters shall be as specified in table II herein. All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit pattern. Steady-state life test conditions, method 1005 of MIL-STD-883. Test condition D or F. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883.
(2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. d. An endurance test, in accordance with method 1033 of MIL-STD-883, shall be added to group C inspection prior to performing the steady-state life test (see 4.3.2c) and extended data retention (see 4.3.2e). Cycling may be block, byte, or page from devices passing group A after the completion of the requirements of 4.2 herein. Initially, two groups of devices shall be formed, cell 1 and cell 2. The following conditions shall be met: (1) (2) Cell 1 shall be cycled at -55C and cell 2 shall be cycled at +125C for a minimum of 10,000 cycles for device types 01-04,06,07,09-12,14,15 and 100,000 cycles for device types 05,08,13, and 16. Perform group A subgroups 1, 7, and 9 after cycling. Form two new cells (cells 3 and 4) for steady-state life and extended data retention. Cell 3 for steady-state life test consists of one-half of the devices from cell 1 and onehalf of the devices from cell 2. Cell 4 for extended data retention consists of the remaining devices from cells 1 and 2. The sample plans for cell 1, cell 2, cell 3, and cell 4 shall individually be the same as for group C, as specified in method 5005 of MIL-STD-883.
(3) e.
Extended data retention shall consist of: (1) (2) All devices shall be programmed with a charge on all memory cells in each device, such that the cell will read opposite the state that the cell would read in its equilibrium state (e.g., worst case pattern, see 4.2a(3)). Unbiased bake for 1000 hours (minimum) at +150C (minimum). The unbiased bake time may be accelerated by using higher temperature in accordance with the Arrhenius Relationship:
AF = acceleration factor (unitless quantity) = t1 / t2
T = temperature in Kelvin (i.e., t1+ 273) t1 = time (hrs) at temperature T1 t2 = time (hrs) at temperature T2 K = Boltzmanns constant = 8.62 x 10-5eV/K using an apparent activation energy (EA) of 0.6 eV. The maximum storage temperature shall not exceed +200C for packaged devices or +300C for unassembled devices.
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234 APR 97
SIZE
A
REVISION LEVEL
5962-88525
SHEET
D
21
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(3)
Read the pattern after bake and perform endpoint electrical tests for table II herein for group C.
4.3.3 Groups D inspections. Group D inspection shall be in accordance with table IV of method 5005 of MIL-STD-883 and as follows: a. b. End-point electrical parameters shall be as specified in table II herein. All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit pattern. TABLE II. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) 1, 7, 9 or 2, 8A, 10 1*, 2, 3, 7*, 8, 9, 10, 11 1, 2, 3, 4**, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10 ,11
Interim electrical parameters (method 5004) Final electrical test parameters (method 5004) Group A test requirements (method 5005) Groups C and D end-point electrical parameters (method 5005)
1/ (*) Indicates PDA applies to subgroups 1 and 7. 2/ Any or all subgroups may be combined when using multifunction testers. 3/ Subgroup 7 and 8 shall consist of writing and reading the data pattern specified in accordance with the limits of table I subgroups 9, 10, and 11. 4/ For all electrical tests, the device shall be programmed to the data pattern specified. 5/ (**) Indicates that subgroup 4 will only be performed during initial qualification and after design or process changes (see 4.3.1c).
4.4 Methods of inspection. MIL-STD-883 and as follows.
Methods of inspection shall be as specified in the appropriate tables of method 5005 of
4.4.1 Voltage and current. All voltages given are referenced to the microcircuit VSS terminal. Currents given are conventional current and positive when flowing into the referenced terminal. 4.4.2 Programming procedure. The following procedure shall be followed when programming (Write) is performed. The waveforms and timing relationships shown on figure 5 (in accordance with appropriate device type) and the conditions specified in table I shall be adhered to. Information is introduced by selectively programming a TTL low or TTL high on each I/O of the address desired. Functionality shall be verified at all temperatures (group A subgroups 7 and 8) by programming all bytes of each device and verifying the pattern used. 4.4.3 Erasing procedure. There are two forms of erasure, chip and byte, whereby all bits or the address selected will be erased to a TTL high. a. Chip erase is performed in accordance with the waveforms and timing relationships shown on figure 8 (in accordance with appropriate device type) and the conditions specified in table I.
SIZE
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234 APR 97
A
REVISION LEVEL
5962-88525
SHEET
D
22
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b.
Byte erase is performed in accordance with the waveforms and timing relationships shown on figures 5, 6, and 7 (in accordance with appropriate device type) and the conditions specified in table I.
4.4.4 Read mode operation. The waveforms and timing relationships shown on figure 4 and the conditions specified in table I shall be applied when reading the device. Pattern verification utilizes the read mode. 4.4.5 Software data protection. Device types 09-16 software data protection offers a method of preventing inadvertent writes (see figure 9). The instructions, waveforms, and timing relationships shown on figures 4, 5, 6, 7, 10, and 11, and the conditions specified in table I shall apply (see 3.10.2). 4.4.5.1 Set software data protection. Device types 09-16 are placed in protected state by writing a series of instructions (see figure 10) to the device. Once protected, writing to the device may only be performed by executing the same sequence of instructions appended with either a byte write operation or page write operation. The waveforms and timing relationships shown on figures 5, 6, and 7 and the test conditions and limits specified in table I shall apply. 4.4.5.2 Reset software data protection. Device types 09-16 protection feature is reset by writing a series of instructions (see figure 11) to the device. The waveforms and timing relationships shown on figures 5, 6, and 7 and the test conditions and limits specified in table I shall apply. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MILHDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990
DSCC FORM 2234 APR 97
SIZE
A
REVISION LEVEL
5962-88525
SHEET
D
23
www..com
STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 05-04-15 Approved sources of supply for SMD 5962-88525 are listed below for immediate acquisition only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ 5962-8852501XA Vendor CAGE number 1FN41 3/ 3/ 5962-8852501YA 1FN41 3/ 3/ 5962-8852501ZA 1FN41 3/ 3/ 5962-8852501UA 1FN41 3/ 3/ 5962-8852502XA 1FN41 3/ 3/ 5962-8852502YA 1FN41 3/ 3/ 5962-8852502ZA 1FN41 3/ 3/ 5962-8852502UA 1FN41 3/ 3/ 5962-8852503XA 1FN41 3/ 3/ See notes at end of table. Page 1 of 5 Vendor similar PIN 2/ AT28C256-35DM/883 DM28C256-350/B X28C256DMB-35 AT28C256-35LM/883 LM28C256-350/B X28C256EMB-35 AT28C256-35FM/883 FM28C256-350/B X28C256FMB-35 AT28C256-35UM/883 TM28C256-350/B X28C256KMB-35 AT28C256-30DM/883 DM28C256-300/B X28C256DMB-30 AT28C256-30LM/883 LM28C256-300/B X28C256EMB-30 AT28C256-30FM/883 FM28C256-300/B X28C256FMB-30 AT28C256-30UM/883 TM28C256-300/B X28C256KMB-30 AT28C256-25DM/883 DM28C256-250/B X28C256DMB-25
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Standard microcircuit drawing PIN 1/ 5962-8852503YA
Vendor CAGE number 1FN41 3/ 3/
Vendor similar PIN 2/ AT28C256-25LM/883 LM28C256-250/B X28C256EMB-25 AT28C256-25FM/883 FM28C256-250/B X28C256FMB-25 AT28C256-25UM/883 TM28C256-250/B X28C256KMB-25 AT28C256-20DM/883 DM28C256-200/B X28C256DMB-20 AT28C256-20LM/883 LM28C256-200/B X28C256EMB-20 AT28C256-20FM/883 FM28C256-200/B X28C256FMB-20 AT28C256-20UM/883 TM28C256-200/B X28C256KMB-20 AT28C256E-25DM/883 DM28C256-250/B X28C256DMB-25 AT28C256E-25LM/883 LM28C256-250/B X28C256EMB-25 AT28C256E-25FM/883 FM28C256-250/B X28C256FMB-25 AT28C256E-25UM/883 AT28C256-15DM/883 DM28C256A-150/B X28C256DMB-15
5962-8852503ZA
1FN41 3/ 3/
5962-8852503UA
1FN41 3/ 3/
5962-8852504XA
1FN41 3/ 3/
5962-8852504YA
1FN41 3/ 3/
5962-8852504ZA
1FN41 3/ 3/
5962-8852504UA
1FN41 3/ 3/
5962-8852505XA
1FN41 3/ 3/
5962-8852505YA
1FN41 3/ 3/
5962-8852505ZA
1FN41 3/ 3/
5962-8852505UA 5962-8852506XA
1FN41 1FN41 3/ 3/
See notes at end of table. Page 2 of 5
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Standard microcircuit drawing PIN 1/ 5962-8852506YA
Vendor CAGE number 1FN41 3/ 3/
Vendor similar PIN 2/ AT28C256-15LM/883 LM28C256A-150/B X28C256EMB-15 AT28C256-15FM/883 FM28C256A-150/B X28C256FMB-15 AT28C256-15UM/883 TM28C256A-150/B X28C256KMB-15 AT28C256F-15DM/883 DM28C256AH-150/B AT28C256F-15LM/883 LM28C256AH-150/B AT28C256F-15FM/883 FM28C256AH-150/B AT28C256F-15UM/883 TM28C256AH-150/B AT28C256E-15DM/883 DM55C256A-150/B X28C256DMB-15 AT28C256E-15LM/883 LM55C256A-150/B X28C256EMB-15 AT28C256E-15FM/883 FM55C256A-150/B X28C256FMB-15 AT28C256E-15UM/883 AT28C256-35DM/883 X28C256DMB-35 AT28C256F-35LM/883 X28C256EMB-35 AT28C256F-35FM/883 X28C256FMB-35
5962-8852506ZA
1FN41 3/ 3/
5962-8852506UA
1FN41 3/ 3/
5962-8852507XA
1FN41 3/
5962-8852507YA
1FN41 3/
5962-8852507ZA
1FN41 3/
5962-8852507UA
1FN41 3/
5962-8852508XA
1FN41 3/ 3/
5962-8852508YA
1FN41 3/ 3/
5962-8852508ZA
1FN41 3/ 3/
5962-8852508UA 5962-8852509XA
1FN41 1FN41 3/
5962-8852509YA
1FN41 3/
5962-8852509ZA
1FN41 3/
See notes at end of table. Page 3 of 5
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Standard microcircuit drawing PIN 1/ 5962-8852509UA
Vendor CAGE number 1FN41 3/
Vendor similar PIN 2/ AT28C256F-35UM/883 X28C256KMB-35 AT28C256-30DM/883 X28C256DMB-30 AT28C256-30LM/883 X28C256EMB-30 AT28C256-30FM/883 X28C256FMB-30 AT28C256-30UM/883 X28C256KMB-30 AT28C256-25DM/883 X28C256DMB-25 AT28C256-25LM/883 X28C256EMB-25 AT28C256-25FM/883 X28C256FMB-25 AT28C256-25UM/883 X28C256KMB-25 AT28C256-20DM/883 X28C256DMB-20 AT28C256-20LM/883 X28C256EMB-20 AT28C256-20FM/883 X28C256FMB-20 AT28C256-20UM/883 X28C256KMB-20 AT28C256E-25DM/883 X28C256DMB-25 AT28C256E-25LM/883 X28C256EMB-25 AT28C256E-25FM/883 X28C256FMB-25
5962-8852510XA
1FN41 3/
5962-8852510YA
1FN41 3/
5962-8852510ZA
1FN41 3/
5962-8852510UA
1FN41 3/
5962-8852511XA
1FN41 3/
5962-8852511YA
1FN41 3/
5962-8852511ZA
1FN41 3/
5962-8852511UA
1FN41 3/
5962-8852512XA
1FN41 3/
5962-8852512YA
1FN41 3/
5962-8852512ZA
1FN41 3/
5962-8852512UA
1FN41 3/
5962-8852513XA
1FN41 3/
5962-8852513YA
1FN41 3/
5962-8852513ZA
1FN41 3/
See notes at end of table. Page 4 of 5
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Standard microcircuit drawing PIN 1/ 5962-8852513UA
Vendor CAGE number 1FN41 3/
Vendor similar PIN 2/ AT28C256E-25UM/883 X28C256KMB-25 AT28C256-15DM/883 X28C256DMB-15 AT28C256-15LM/883 X28C256EMB-15 AT28C256-15FM/883 X28C256FMB-15 AT28C256-15UM/883 X28C256KMB-15 AT28C256F-15DM/883 AT28C256F-15LM/883 AT28C256F-15FM/883 AT28C256-15UM/883 AT28C256E-15DM/883 X28C256DMB-15 AT28C256E-15LM/883 X28C256EMB-15 AT28C256E-15FM/883 X28C256FMB-15 AT28C256E-15UM/883
5962-8852514XA
1FN41 3/
5962-8852514YA
1FN41 3/
5962-8852514ZA
1FN41 3/
5962-8852514UA
1FN41 3/
5962-8852515XA 5962-8852515YA 5962-8852515ZA 5962-8852515UA 5962-8852516XA
1FN41 1FN41 1FN41 1FN41 1FN41 3/
5962-8852516YA
1FN41 3/
5962-8852516ZA
1FN41 3/
5962-8852516UA 1/ 2/ 3/
1FN41
The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Not available from an approved source. Vendor CAGE number 1FN41 Vendor name and address ATMEL Corporation 2325 Orchard Parkway San Jose, CA 95131
The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.
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